Methods and apparatus for providing direct memory access control

ABSTRACT

Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical processing element (PE) identifier translation is employed in conjunction with a ManArray PE interconnection topology to support a variety of communication models, such as hyper-cube and such. Also, PE addressing nodes are based upon logically nested parameterized loops. Mechanisms for updating loop parameters, as well as exemplary instruction formats are also described.

RELATED APPLICATIONS

More than one reissue application has been filed for the reissue of U.S.Pat. No. 6,453,367. The reissue applications are application Nos.10/819,885 which is the present application and 11/526,296 which is thedivisional reissue application filed concurrently herewith.

The present application is a division of U.S. application Ser. No.09/472,372 filed Dec. 23, 1999, now U.S. Pat. No. 6,256,683, which inturn claimed the benefit of U.S. Provisional Application Ser. No.60/113,637 entitled “Methods and Apparatus for Providing Direct MemoryAccess (DMA) Engine” and filed Dec. 23, 1998 which is incorporated byreference in its entirety herein.

FIELD OF THE INVENTION

The present invention relates generally to improvements in arrayprocessing, and more particularly to advantageous techniques forproviding improved mechanisms of data distribution to, and collectionfrom multiple memories often associated with and local to processingelements within an array processor.

BACKGROUND OF THE INVENTION

Various prior art techniques exist for the transfer of data betweensystem memories or between system memories and I/O devices. FIG. 1 showsa conventional data processing system 100 comprising a host uniprocessor110, processor local memory 120, direct memory access (DMA) controller160, system memory 150 which is usually a larger memory store than theprocessor local memory, having longer access latency, and input/output(I/O) devices 130 and 140.

The DMA controller 160 provides a mechanism for transferring databetween processor local memory and system memory or I/O devicesconcurrent with uniprocessor execution. DMA controllers are sometimesreferred to as I/O processors or transfer processors in the literature.System performance is improved since the host uniprocessor can performcomputations while the DMA controller is transferring new input data tothe processor local memory and transferring result data to outputdevices or the system memory. A data transfer is typically specifiedwith the following minimum set of parameters: source address,destination address, and number of data elements to transfer. Addressesare interpreted by the system hardware and uniquely specify I/O devicesor memory locations from which data must be read or to which data mustbe written. Sometimes additional parameters are provided such as elementsize. One of the limitations of conventional DMA controllers is thataddress generation capabilities for the data source and data destinationare often constrained to be the same. For example, when only a sourceaddress, destination address and a transfer count are specified, theimplied data access pattern is block-oriented, that is, a sequence ofdata words from contiguous addresses starting with the source address iscopied to a sequence of contiguous addresses starting at the destinationaddress. Array processing presents challenges for data collection anddistribution both in terms of addressing flexibility, control andperformance. The patterns in which data elements are distributed andcollected from processing element local memories can significantlyaffect the overall performance of the processing system. With the adventof the ManArray architecture it has been recognized that it will beadvantageous to have improved techniques for data transfer which providethese capabilities and which are tailored to this new architecture.

SUMMARY OF THE INVENTION

As described in detail below, the present invention addresses a varietyof advantageous methods and apparatus for improved data transfer controlwithin a data processing system. In particular we provide improvedtechniques for: distributing data to, and collecting data from an arrayof processing elements (PEs) in a flexible and efficient manner; and PEaddress translation which allows data distribution and collection basedon PE virtual IDs.

Further aspects of the present invention are related to avirtual-to-physical PE ID translation which works together with aManArray PE interconnection topology to support a variety ofcommunication models (such as hypercube and mesh) through data placementbased upon a PE virtual ID. This result can be accomplished in a DMAcontroller by translation, through a VID-to-PID lookup table or throughcombinational logic, where the resulting PID becomes an addressingcomponent on the DMA bus to PE local memories. This result can also beachieved at the PE local memories within the interface logic, where aVID available to the interface logic is compared to a VID presented onthe DMA bus. A match at a particular memory interface allows that memoryto accept the access. The present invention also addresses the provisionof PE addressing modes based on generating data access patterns fromlogically nested parameterized loops. Varying assignments of loopparameters to nesting level allows flexible data access patterns to begenerated. Providing varying mechanisms for updating loop parametersprovides greater flexibility for generating complex-periodic accesspatters patterns, such as select-index modes which provide a table ofindex-update values which are used when the index loop parameter isupdated; select-PE modes which provide a table of bit-vector controlvalues, each of which specifies the PEs to be accessed for an iterationthrough the “PE update loop” (i.e., the loop which PE update isassigned); and select-index-PE modes which provide both select-index andselect-PE update capability and combine to form the most flexible modefor generating complex-periodic data access patterns. Further, theinvention addresses the design of a looping mechanism to be reentrantthereby allowing any addressing mode to be restarted after completing aspecific number of element transfers, by just loading or reloading a newtransfer count and continuing the transfer. This result is accomplishedby initializing addressing parameters at instruction load time, and onlyupdating them after a loop exits.

These and other advantages of the present invention will be apparentfrom the drawings and the Detailed Description which follow.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a conventional data processing system with a DMA controllerto support data transfers concurrent with host processor computation;

FIG. 2 illustrates a ManArray DSP with a DMA controller in arepresentative system in accordance with the present invention;

FIG. 3 illustrates a DMA controller implemented as a multiprocessor,with two transfer controllers, bus connections to a system memory, PEmemories and a control bus;

FIG. 4 shows a single transfer controller comprising 4 primary executionunits, bus connections and FIFO buffers;

FIG. 5 shows an exemplary format of a transfer type instruction inaccordance with the present invention;

FIG. 6 shows an exemplary virtual PE identification to physical PEidentification (VID-to-PID) translation;

FIG. 7 shows an exemplary logical implementation of VID-to-PIDtranslation;

FIG. 8 shows an exemplary PEXLAT instruction (“load VID-to-PID table”);

FIG. 9 illustrates a VID-to-PID translation table register, called thePETABLE register in a presently preferred embodiment;

FIG. 10 illustrates a nested logical loop model showing a “BIP”assignment of address components to loops: base (outer), index (middle)and PE VID (inner);

FIG. 11 shows a nested logical loop model with “BPI” assignment ofaddress components to loops: base (outer), PE (middle) and index(inner);

FIG. 12 is a nested logical loop model showing a “PBI” assignment ofaddress components to loops: PE (outer), Base (middle) and Index(inner);

FIG. 13 illustrates an exemplary format for a PE Block-cyclicinstruction in accordance with the present invention;

FIG. 14 shows an exemplary transfer result using PE Blockcyclic addressmode with BIP loop assignment;

FIG. 15 shows an exemplary transfer result using PE Blockcyclic addressmode with BPI loop assignment;

FIG. 16 shows an exemplary transfer result using PE Blockcyclic addressmode with PBI loop assignment;

FIG. 17 illustrates an exemplary format for a PE Select-Index transferinstruction in accordance with the present invention;

FIG. 18 shows an exemplary transfer result using a PE Select-Indexaddress mode with BIP loop assignment;

FIG. 19 illustrates an exemplary format for a PE Select-PE transferinstruction in accordance with the present invention;

FIG. 20 shows an exemplary transfer result using a PE Select-PE addressmode with BIP loop assignment;

FIG. 21 illustrates an exemplary format for a PE Select-Index-PEtransfer instruction in accordance with the present invention; and

FIG. 22 shows an exemplary transfer result using a PE Select-Index-PEaddress mode with BIP loop assignment.

DETAILED DESCRIPTION

Further details of a presently preferred ManArray core, architecture,and instructions for use in conjunction with the present invention arefound in U.S. patent application Ser. No. 08/885,310 filed Jun. 30,1997, now U.S. Pat. No. 6,023,753, U.S. patent application Ser. No.08/949,122 filed Oct. 10, 1997, now U.S. Pat. No. 6,167,502, U.S. patentapplication Ser. No. 09/169,255 filed Oct. 9, 1998, U.S. patentapplication Ser. No. 09/169,256 filed Oct. 9, 1998, now U.S. Pat. No.6,167,501, U.S. patent application Ser. No. 09/169,072 filed Oct. 9,1998, now U.S. Pat. No. 6,219,776, U.S. patent application Ser. No.09/187,539 filed Nov. 6, 1998, now U.S. Pat. No. 6,151,668, U.S. patentapplication Ser. No. 09/205,558 filed Dec. 4, 1998, now U.S. Pat. No.6,173,389, U.S. patent application Ser. No. 09/215,081 filed Dec. 18,1998, now U.S. Pat. No. 6,101,592, U.S. patent application Ser. No.09/228,374 filed Jan. 12, 1999, now U.S. Pat. No. 6,216,223, U.S. patentapplication Ser. No. 09/238,446 filed Jan. 28, 1999, U.S. patentapplication Ser. No. 09/267,570 filed Mar. 12, 1999, U.S. patentapplication Ser. No. 09/337,839 filed Jun. 22, 1999, U.S. patentapplication Ser. No. 09/350,191 filed Jul. 9, 1999, U.S. patentapplication Ser. No. 09/422,015 filed Oct. 21, 1999, U.S. patentapplication Ser. No. 09/432,705 filed Nov. 2, 1999, U.S. patentapplication Ser. No. 09/471,217 filed Dec. 23, 1999, now U.S. Pat. No.6,260,082, as well as, Provisional Application Ser. No. 60/139,946entitled “Methods and Apparatus for Data Dependent Address Operationsand Efficient Variable Length Code Decoding in a VLIW Processor” filedJun. 18, 1999, Provisional Application Ser. No. 60/140,245 entitled“Methods and Apparatus for Generalized Event Detection and ActionSpecification in a Processor” filed Jun. 21, 1999, ProvisionalApplication Ser. No. 60/140,163 entitled “Methods and Apparatus forImproved Efficiency in Pipeline Simulation and Emulation” filed Jun. 21,1999, Provisional Application Ser. No. 60/140,162 entitled “Methods andApparatus for Initiating and Re-Synchronizing Multi-Cycle SIMDInstructions” filed Jun. 21, 1999, Provisional Application Ser. No.60/140,244 entitled “Methods and Apparatus for Providing One-By-OneManifold Array (1×1 ManArray) Program Context Control” filed Jun. 21,1999, Provisional Application Ser. No. 60/140,325 entitled “Methods andApparatus for Establishing Port Priority Function in a VLIW Processor”filed Jun. 21, 1999, Provisional Application Ser. No. 60/140,425entitled “Methods and Apparatus for Parallel Processing Utilizing aManifold Array (ManArray) Architecture and Instruction Syntax” filedJun. 22, 1999, Provisional Application Ser. No. 60/165,337 entitled“Efficient Cosine Transform Implementations on the ManArrayArchitecture” filed Nov. 12, 1999, and Provisional Application Ser. No.60/171,911 entitled “Methods and Apparatus for Loading of Very LongInstruction Word Memory” filed Dec. 23, 1999, respectively, all of whichare assigned to the assignee of the present invention and incorporatedby reference herein in their entirety.

The following definitions of terms are provided as background for thediscussion of the invention which follows:

A “transfer” refers to the movement of one or more units of data from asource device (either I/O or memory) to a destination device (I/O ormemory).

A data “source” or “destination” refers to a device from which data maybe read or to which data may be written which is characterized by acontiguous sequence of one or more addresses, each of which isassociated with a data storage element of some unit size. For some datasources and destination there is a many-to-one mapping of addresses todata element storage locations. For example, an I/O device may beaccessed using one of many addresses in a range of addresses, yet itwill perform the same operation, such as returning the next data elementof a FIFO, for any of them.

A “data access pattern” is a sequence of data source or destinationaddresses whose relationship to each other is periodic. For example, thesequence of addresses 0, 1, 2, 4, 5, 6, 8, 9, 10, . . . etc. is a dataaccess pattern. If we look at the differences between successiveaddresses, we find: 1,1,2, 1,1,2, 1,1,2, . . . etc. Every three elementsthe pattern repeats.

An “address mode” or “addressing mode” refers to a rule that describes asequence of addresses, usually in terms of one or more parameters. Forexample, a “block” address mode is described by the rule:address[i]=base_address+i where i=0, 1, 2, . . . etc. and wherebase_address is a parameter and refers to the starting address of thesequence.

Another example is a “stride” address mode which may be described by therule:address[i]=base_address+(i mod(stride−hold))+(i/hold)*stridefor i=0, 1, 2, . . . etc., and where base_address, stride and hold areparameters, and where division is integer division in which anyremainder is discarded.

An “address generation unit (AGU)” is a hardware module that generates asequence of addresses (a data access pattern) according to a programmedaddress mode.

“EOT” means “end-of-transfer” and refers to the state when a transferexecution unit (described in the following text) has completed its mostrecent transfer instruction by transferring the number of elementsspecified by the instruction's transfer count field.

The term “host processor” as used in the following description is anyprocessor or device which can write control commands and read statusfrom the DMA controller and/or which can respond to DMA controllermessages and signals. In general, a host processor interacts with a DMAcontroller to control and synchronize the flow of data between devicesand memories in the system in such a way as to avoid overrun andunderrun conditions at the sources and destinations of data transfers.

The present invention provides a set of flexible addressing modes forsupporting efficient data transfers to and from multiple memories,together with methods and apparatus for allowing data accesses to bedirected to PEs according to virtual as opposed to physical IDs. Thissection describes an exemplary DMA controller and a system environmentin which the present inventions may be effectively used. The followingsections describe PE memory addressing, virtual-to-physical PE IDtranslation and its purpose, and a set of PE memory addressing modes or“PE addressing modes” which support numerous parallel algorithms withhighly efficient data transfer.

FIG. 2 shows an exemplary system 200 illustrating the context in which aManArray DMA controller 201, in accordance with the present invention,resides. The DMA controller 201 accesses processor local memories 210,211, 212, 213, 214 and 215 via a DMA Bus 202, 202 ₁, 202 ₂, 202 ₃, 202₄, 202 ₅ and memory interface units 205, 206, 207, 208 and 209 to whichit is connected. A ManArray DSP 203 also connects to its local memories210-215 via memory interface units 205-209. Further details of apresently preferred DSP 203 are found in the above incorporated byreference applications.

In this representative system, the DMA controller also connects to twosystem busses, a system control bus (SCB) 235 and a system data bus(SDB) 240. The DMA controller is designed to transfer data betweendevices on the SDB 240, such as a system memory 250 and the DSP 203local memories 210-215. The SCB 235 is used by an SCB master such as theDSP 203 or a host control processor (HCP) 245 to program the DMAcontroller 201 with read and write addresses and registers to initiatecontrol operations and read status. The SCB 235 is also used by the DMAcontroller 201 to send synchronization messages to other SCB bus slavessuch as the DSP control registers 225 and a host I/O block 255. Someregisters in these slaves can be polled by the DSP and HCP to receivestatus from the DMA. Alternatively, DMA writes to some of these slaveaddresses can be programmed to cause interrupts to the DSP and/or HCPallowing DMA controller messages to be handled by interrupt serviceroutines.

FIG. 3 shows a system 300 which illustrates operation of a DMAController 301 which may suitably be a multiprocessor specialized tocarry out data transfers utilizing one or more transfer controllers 302and 303. Each transfer controller can operate as an independentprocessor or work together with other transfer controllers to carry outdata transfers. The DMA busses 305 and 310 provide, in the presentlypreferred embodiment, independent data paths to local memories 320, 321,322, 323, 324, 325, one for each transfer controller 302 and 303. Inaddition, each transfer controller is connected to SDB 350 and to SCB330. Each transfer controller operates as a bus master and a bus slaveon both the SCB and SDB. As a bus slave on the SCB, a transfercontroller may be accessed by other SCB bus masters in order to read itsinternal state or to issue control commands. As a bus master on the SCB,a transfer controller can send synchronization messages to other SCB busslaves. As a bus master on the SDB, a transfer controller performs datareads and writes from or to system memory or I/O devices which are busslaves on the SDB. As a bus slave on the SDB, a transfer controller cancooperate with another SDB bus master in a “slave mode” allowing the busmaster to read or write data directly from or to its data FIFOs (asdiscussed further below). It may be noted that the DMA busses 305 and310, the SDB 350 and the SCB 330 may be implemented in different ways.For example, they may be implemented with varying bus widths, protocols,or the like consistent with the teachings of the present invention.

FIG. 4 shows a system 400 having single transfer controller 401comprising a set of execution units including an instruction controlunit (ICU) 440, a system transfer unit (STU) 402, a core transfer unit(CTU) 408 and an event control unit (ECU) 460. An inbound data queue(IDQ) 405 is a data FIFO buffer which is written with data from an SDB470 under control of the STU 402. Data is read from the IDQ 405 undercontrol of the CTU 408 to be sent to core memories 430, or sent to theICU 440 in the case of instruction fetches. An outbound data queue (ODQ)406 is a data FIFO which is written with data from DMA busses 425 undercontrol of the CTU 408, to be sent to an SDB 470 device or memory underthe control of the STU 402. The CTU 408 may also read DMA instructionsfrom a memory attached to the DMA bus, which are forwarded to the ICU440 for initial decoding. The ECU 460 receives signal inputs fromexternal devices 465, commands from the SCB 450 and instruction datafrom the ICU 440. It generates output signals 435, 436 and 437 which maybe used to generate interrupts on host control processors within thesystem, and can act as a bus master on the SCB 450 to sendsynchronization messages to SCB bus slaves.

Each transfer controller within a ManArray DMA controller is designed tofetch its own stream of DMA instructions. DMA instructions are of fivebasic types: transfer; branch; load; synchronization; and state control.The branch, load, synchronization, and state control types ofinstructions are collectively referred to as “control instructions”, anddistinguished from the transfer instructions which actually perform datatransfers. DMA instructions are typically of multi-word length andrequire a variable number of cycles to execute although several controlinstructions require only a single word to specify. Although thepresently preferred embodiment supports multiple DMA instruction typesas described in further detail in U.S. patent application Ser. No.09/471,217 filed Dec. 23, 1999, now U.S. Pat. No. 6,260,082, andincorporated by reference in its entirety herein, the present inventionfocuses on instructions and mechanisms which provide for flexible andefficient data transfers to and from multiple memories.

Referring further to system 400 of FIG. 4, transfer-type instructionsare dispatched by the ICU for further decoding and execution by the STU402 and the CTU 408. Transfer instructions have the property that theyare fetched and decoded sequentially, in order to load transferparameters into the appropriate execution unit, but are executedconcurrently. The control means for initiating execution of transferinstructions is a flag bit contained in the instruction itself, and isdescribed below.

A “transfer-system-inbound” (TSI) instruction moves data from the SDB470 to the IDQ 405 and is executed by the STU. A “transfer-core-inbound”(TCI) instruction moves data from the IDQ 405 to the DMA Bus 425 and isexecuted by the CTU. A “transfer-core-outbound” (TCO) instruction movesdata from the DMA Bus 425 to the ODQ 406 and is executed by the CTU. A“transfer-system-outbound” (TSO) instruction moves data from the ODQ 406to the SDB 470 and is executed by the STU. Two transfer instructions arerequired to move data between an SDB system memory and one or more SP orPE local memories on the DMA bus, and both instructions are executedconcurrently: a TSI, TCI pair or a TSO, TCO pair.

The address parameter of STU transfer instructions TSI and TSO refers toaddresses on the SDB while the address parameter of CTU transferinstructions refers to addresses on the DMA bus to PE and SP localmemories.

FIG. 5 shows an exemplary instruction format 500 for transferinstructions. A base opcode field 501 indicates that the instruction isof transfer type. A C/S field 510 indicates the transfer unit (CTU orSTU) and I/O field 520 indicates whether the transfer direction isinbound or outbound. The execute (“X”) field 550 is a field which, whenset to “1”, indicates a “start transfer” event, that is, that thetransfer should start immediately after loading the transferinstruction. When the “X” field is “0”, then the parameters are loadedinto the specified unit but the transfer is not initiated. Instructionfetch/decode continues normally until a “start transfer” event occurs. Adata type field 530 indicates the size of each element transferred andan address mode 540 refers to the data access pattern which must begenerated by the transfer unit. A transfer count 560 indicates thenumber of data elements of size “data type” which are to be transferredto or from the target memory/device before EOT occurs for that unit. Anaddress parameter 570 specifies the starting address for the transfer.Other parameters 580 may follow the address word of the instruction,depending on the addressing mode used.

While there are six memories 210, 211, 212, 213, 214, and 215 shown inFIG. 2, the PE address modes access only the set of PE memories 210,211, 212 and 213 in this exemplary ManArray DSP configuration. Theaddress of a data element within PE local memory space is specified withthree variables, a PE ID, a base value and an index value. The base andthe index values are summed to form an offset into a PE memory relativeto an address 0, the first address of that PE's memory. The address of aPE data element is therefore given by a pair: PE data address=(PE ID,Base+Index).

The ManArray architecture supports a unique interconnection networkbetween processing elements (PEs) which uses PE virtual IDs (VIDs) tosupport useful single-cycle communication paths, for example, torus orhypercube paths. In some array organizations, the PE's physical andvirtual IDs are equal. The VIDs are used in the architecture to specifythe pattern for data distribution and collection. When data isdistributed according to the pattern established by VID assignment, thenefficient inter-PE communication required by the programmer becomesavailable. As an example, if a programmer needs to establish a hypercubeconnectivity for a 16 PE ManArray processor, the data will bedistributed according to a VID assignment in such a manner that thephysical switch connections allow data to be transferred between PEs asthough the switch topology were a hypercube even if the switchconnections between physical PEs do not support the fill hyper-cubeinterconnect. The present invention describes two approaches whereby theDMA controller can access PE memories according to their VIDs,effectively mapping PE virtual IDs to PE physical IDs (PIDs). The firstuses VID-to-PID translation within the CTU of a transfer controller.This translation can be performed either through table-lookup, orthrough logic permutations on the VID. The second approach associates aVID with a PE by providing a programmable register within the PE or thePE local memory interface unit (LMIU), FIG. 2 205, 206, 207 and 208which is used by the LMIU logic to “capture” a data access when its VIDmatches a VID provided on the DMA Bus for each DMA memory access.

VID to PID Translation within the DMA Controller

With this approach, a PE VID-to-PID table is maintained in the DMAcontroller so that data may be distributed to the ManArray according toa programmer's view of the array. In the preferred embodiment, thistable is maintained in the CTU of each transfer controller. FIG. 6 showsan exemplary mapping table 600 of VID into PID for a four PE system,such as a ManArray 2×2 system. The VIDs are in column 602 on the leftand their corresponding PIDs are shown in column 604 on the right. Anexample of a table lookup implementation of the mapping of FIG. 6 isillustrated logically as system 700 of FIG. 7. In the presentlypreferred embodiment, a translation table 710 is stored in the CTU of atransfer controller. A CTU transfer instruction 705 (TCI or TCO)specifies a starting address 775 which is used by AGU 770 to generate aninitial VID 720. The VID 720 controls the selection of one of theelements of the VID-to-PID lookup table 710 through multiplexer 715which is then sent to a DMA Bus 740 as the PE ID component of the PEaddress. The numbers on the multiplexer 715 indicate the VID value whichmust be applied to select the corresponding input. Successive VIDs aregenerated by the AGU 770, possibly in a recursive fashion as shown byfeedback 708. At the same time, the AGU 770 generates a sequence of PEmemory offsets 730, also possibly using recursive feedback 755. The PEmemory offset 750 is also sent to the DMA bus as a second component of aPE address. Logic in the local memory interface units (LMIUs) is used tocompare the PE ID sent on the DMA bus to a stored PID (hard-coded) forany DMA bus access. If this matches, then the LMIU accepts the accessand accepts write data or returns read data.

The approach of FIG. 7 has the advantage that all mappings of PE VIDs toPIDs are supported. With larger numbers of PE local memories, theregister or memory space required to store this table grows. Forexample, a 16 PE memory system requires 64 bits of register or memoryspace to store the PIDs. An alternative approach to table lookup-basedtranslation is to provide logic which performs a subset of allVID-to-PID mappings. This translation logic would also be parameterized,but would require significantly fewer bits to configure. As a simpleexample, let the PID be formed by complementing any bit of the VID. Ifthe PID and VID require 4 bits to represent the needed IDs, say for a 16PE system, then a four bit “translation vector” (XVEC) must be stored toconfigure the translation rather than the 64 bits for table lookup. ThePID is obtained from the VID by the following: PID=VID xor XVEC. Thatis, each bit of VID is exclusive-or'd with the corresponding bit ofXVEC. The set of PIDs resulting from applying this operation to each VIDconstitutes the mapping. Obviously, the number of mappings available isfar fewer than with a table lookup approach, but for systems with alarge number of PE memories, only a few mappings may be required tosupport the desired communication patterns.

In the presently preferred embodiment, a lookup table is used to performthe VID-to-PID translation. Two approaches are provided for initializingthe translation table. The first is through a DMA instruction 800, shownin FIG. 8. When executed, DMA instruction 800 loads a PETABLE register900 which is illustrated in FIG. 9. The second approach is through adirect write of the PETABLE register 900 via the SCB.

PE Virtual IDs Stored in Local Memory Interface Units

The second approach to directing data access according to PE VID relieson distributing the PE VIDs to each PE local memory interface unit(LMIU). The VID for each PE might reside in a register either in the PEitself or in its LMIU. In this case, there is no translation table orlogic in the DMA lane controllers. In common with the precedingapproach, there is a PE ID component of the DMA bus which is driven bythe transfer controllers and used by the LMIUs to compare for a matchwith the locally visible PE VID. When a match is detected in a PE, thenit accepts the access which may be either a write or a read request.Means for updating the VIDs stored locally in the LMIUs may be providedthrough the use of registers visible in the PE register address space,or through a PE instruction which broadcasts the table to all PEs, whothen select their VID using their hard-coded PID stored locally. Thisapproach has advantages when VIDs are used for other purposes than justdata distribution and collection by a DMA controller.

CTU Addressing Modes

A CTU 408 shown in FIG. 4 supports a basic set of address modes whichmay be used to target memories associated with each PE or SPindividually. These address modes include single-address, block, strideand circular modes. These addressing modes will not be described indetail herein, but are a common set of addressing modes used for manyuniprocessor applications. In addition to these address modes, the CTU408 provides a set of “PE address modes” which allow data to bedistributed across or collected from multiple PE memories in a varietyof patterns. These address modes are based on a software model ofaddress generation based on parameterizable loops, which is thenimplemented in hardware.

Flexible PE Addressing Modes through Parameterizable Logical Loops

Many algorithms which are distributed across multiple PEs requirecomplex data access patterns to achieve peak efficiency. The basis forour loop-based PE addressing modes is a logical view of data accessconsisting of a set of nested loops in which one component of the PEmemory address is assigned to be updated at the end of each loop. Asstated above, a PE memory address consists of three components called“address components”, a PE virtual ID (VID), a base value (Base) and anindex value (Index). This model requires the following: a mechanism forassigning address components to logical loops; a mechanism forinitializing address components; and a mechanism for updating addresscomponents; and a mechanism for indicating a loop's exit condition.

Assignment of an address component to a loop specifies the order inwhich the three address components are updated. In an embodiment whichuses a three-loop model, there are six possible orders for updatingaddress components (i.e., six ways to re-order VID, Base and Index). Thebase and index components are defined to be ordered in this embodimentso that the index is always updated prior to the base, which reduces thenumber of possible orderings to three, since base and index are summedto form an offset into PE memory, allowing loop assignments that updatethe base before the index is redundant. An exemplary loop assignment is:update VID on inner loop; update index on middle loop; and update baseon outer loop.

Thus, as PE addresses are generated, the VID component updates first(inner loop). When all VIDs have been used (VID loop exit condition hasbeen reached), then the VID is reinitialized, the index is updated, andthe VID loop is reentered. This looping continues until the number ofindex updates is exhausted (Index loop exit condition has been reached)at which point the index is reinitialized, the base is updated, theindex loop is reentered, then the VID loop is reentered. This furtherlooping continues until the transfer count is exhausted.

Updating an address component is performed by selecting a new value forthe component either based on the old value (e.g. new=old+1) or by someother means, such as by table lookup. A loop exit condition specifieswhat causes the loop to exit to the next-most outer loop in the model.

In summary, three different aspects of loop control are used to vary thesequence in which PE memories may be accessed. These are:

-   -   (1) Rearranging the order of assignment of address components to        logical loops,    -   (2) Varying the method for updating the address components, and    -   (3) Varying the loop termination conditions.

FIGS. 10, 11 and 12 show logical representations or processes 1000, 1100and 1200, respectively, of preferred assignments of address parameters(PE VID, Base and Index) to logical loops. In the nomenclature used inFIGS. 10, 11 and 12, the term “PE” refers to the PE VID component of aPE address. In FIG. 10, the address components are assigned in “Base,Index, PE” (BIP) ordering. This means that the PE is updated in theinnermost loop, the index parameter is updated in the “middle” loop andthe base parameter is updated in the “outer” loop. In FIG. 11, the loopassignments are in a “Base, PE, Index” (BPI) ordering, and in FIG. 12,the loop assignments are in a “PE, Base, Index” (PBI) ordering.

FIG. 10 shows a logical representation 1000 of the nested loop model inwhich the PE VID is updated in an inner loop 1030, the index is updatedin a middle loop 1020, and the base is updated in an outer loop 1010. Afourth loop 1005 which encompasses the other three loops indicates thatthe other loops are continued until the number of data elementsspecified in the transfer instruction have been accessed. Associatedwith each loop is a condition for loop exit 1010, 1020 or 1030,respectively, where the “!” character represents a logical NOT. Alsoassociated with each loop is a mechanism 1060, 1070 or 1077,respectively, for updating the loop address parameter and for testingthe updated value to indicate whether the exit condition for that loophas become TRUE. Prior to starting any loop is an address initializationblock 1002 which sets the starting values of each address component (PE,Base and Index). The data transfer implemented by FIG. 10 will cause PEsto be accessed first until an “exit PE loop” condition has become true(PELoopComplete is TRUE), at which point the PE loop exits and the PEparameter is reinitialized in step 1065. The index parameter is thenupdated and tested for its terminal condition in step 1070. If the indexparameter's terminal condition has not become TRUE, then the PE loop isreentered. When the index parameter's terminal condition becomes TRUE,the index loop is exited, the index parameter is reinitialized in step1075 and the base parameter is updated and tested for a terminalcondition in step 1080. If the base parameter terminal condition has notbeen reached, then the index and PE loops are reentered and executeduntil either all data items have been accessed (transfer count specifiedin the transfer instruction becomes zero) or the index loop isterminated again. When BaseLoopComplete becomes TRUE, the base value isreinitialized in step 1085 and the loops are reentered again.

FIGS. 11 and 12 show nested logical loops or processes 1100 and 1200corresponding to “BPI” access (index is updated first, followed by PE,followed by base) and “PBI” access (Index is updated first, followed byBase, then lastly PE) respectively.

The following aspects of the loop formulation are noted. When therequested number of accesses are made (TC in FIGS. 10-12) then all loopsare exited immediately, leaving all address and loop control variablesin their current states. By using logical “while” loops andreinitializing a loop only at its exit, it is possible to reenter theloops and continue a transfer after “terminal count” (TC) addresses havebeen accessed. This capability is used in this invention to allowtransfers to be restarted so that the addressing continues as though itwould if the transfer count had not been exhausted. For further detailsof such transfers see U.S. application Ser. No. 09/471,217 filed Dec.23, 1999, now U.S. Pat. No. 6,260,082, which is incorporated byreference in its entirety herein.

The functions used to update an address (see UpdateAddress( ) in FIG. 10steps 1060, 1070 and 1077; in FIG. 11 steps 1160, 1170 and 1177; and inFIG. 12 steps 1260, 1270 and 1277) may update the address using aconstant increment value, or a value extracted from a table, or use aselection mechanism based on a bit vector. While other UpdateAddress( )functions might be supported, those listed are supported in thepresently preferred embodiment.

The function used to update the loop control variable,UpdateLoopControl( ), may be performed as part of the address update oras a separate operation as shown in FIGS. 10-12. This operation is usedto update variables which control loop termination. In the preferredembodiment, the control variables are counters or special logicalfunctions consisting of priority encoders and counter blocks.

The function used to check for loop termination simply tests the looptermination variable for an end of loop condition. This condition may bea particular count value or the state of a mask register.

The initialization of address parameters (see Initialize( ) function:FIG. 10 1002, FIG. 11 1102, and FIG. 12 1202) does not necessarily occureach time a transfer is started. In the preferred embodiment, thisinitialization occurs only when a transfer instruction is decoded andparameters are loaded into CTU registers in the case of PE addressingmodes or STU registers.

The following discussion addresses instruction formats and describes PEaddressing modes for one embodiment of the invention. It will berecognized other instruction encodings may be used consistent with theteachings of the present invention. In the preferred embodiment, atransfer controller reads transfer instructions from a local memory anddecodes them. Transfer instructions come in two types, those for the STUand those for the CTU. The STU transfer instructions specify theaddressing mode and transfer count for accesses to the system data buswhile CTU transfer instructions specify the addressing mode and transfercount for accesses to the DMA bus and all SP and PE memories. Theinstruction formats addressed below are only those instructions whichcontrol special PE memory addressing for the CTU. Instruction mnemonicsare used to indicate the instruction type and addressing mode. “TCI”stands for “transfer, core-inbound”, while “TCO” stands for “transfer,core-outbound”. “TCx” stands for either TCI or TCO. The following PEaddressing modes are described as illustrative of the present invention:PE Block-Cyclic, PE Select-Index, PE Select-PE, and PE Select-Index-PE.

PE Block-Cyclic Addressing

PE blockcyclic addressing provides the basic framework for all of the PEaddressing modes. A Loop parameter specifies the assignment of addresscomponents to loops: BIP, BPI, or PBI. FIG. 13 shows an exemplary format1300 which defines the parameters for a PE Blockcyclic transferinstruction executed by the CTU. As an example, if we are given:

-   -   An inbound sequence of 16 data elements with values 0,1,2,3, . .        . 15;    -   PETABLE setting of 0×000000E4 (no translation of PE IDs);    -   TSI.block instruction in the STU (reading the 16 values from        system memory); and    -   TCI.blockcyclic instruction in the CTU with PE count=4, Base        Update=8, Base Count=2 (used for PBI mode only), Index Update=2,        Index Count=2, then the resulting data in the PE memories 1400        after the transfer are shown in FIG. 14 for BIP loop assignment.        FIG. 15 shows resulting data 1500 for BPI loop assignment. FIG.        16 shows resulting data 1600 for PBI loop assignment.        PE Select-Index Addressing

The operation of the PE select-index address mode is similar to the PEblockcyclic address mode except that rather than updating the indexcomponent of the address by adding a constant to it, the instructionspecifies a table of index update values which are used sequentially toupdate the index. FIG. 17 shows an exemplary instruction format 1700 forthe PE select-index instruction.

An index select parameter allows finer-grained control over a sequenceof index values to be accessed. In the example, this is done using atable of eight 4-bit index-update (IU) values. Each time the index loopis updated, an IU value is added to the effective address. These updatevalues are accessed from the table sequentially starting from IU0 forIUCount updates. After IUCount updates, the index update loop iscomplete and the next outer loop (B or P) is activated. On the nextentry of the index loop, IU values are accessed starting at thebeginning of the table. FIG. 18 shows an exemplary data access table1800 illustrating data access using the PE select-index instruction.

PE Select-PE Addressing

The operation of the PE Select-PE address mode is similar to the PEblockcyclic address mode except that rather than updating the PE VIDcomponent of the address by adding 1 to it, the instruction specifies atable of bit vectors, where each bit vector specifies the PE's to selectfor access. A bit set to “1” in a bit vector indicates, by its bitposition, the VID of the PE to access. Bits in each bit vector arescanned from right to left (least to most significant when viewed in afirst instruction format such as instruction format 1900 of FIG. 19).When there are no more “1” bits in a vector, the PE loop exits. The nextiteration of the loop uses the next bit vector in the table. FIG. 19shows an exemplary instruction format 1900, and FIG. 20 shows anexemplary transfer data access table 2000 for a transfer using thisinstruction.

The PE select fields together with the use of the PE translate tableallow out of order access to PEs across multiple passes through them.

PE Select-Index-PE Addressing

This addressing mode combines both select-index and select-PEaddressing. An exemplary instruction format 2100 is shown in FIG. 21.This form of addressing provides for complex-periodic data accesspatterns. An exemplary access pattern table 2200 for thePE-select-index-PE address mode is shown in FIG. 22.

1. An apparatus for performing virtual identification (VID) to physicalidentification (PID) translation for data elements to be accessed withinlocal memory of a processing element (PE) whereby a direct memory access(DMA) controller can access PE local memories according to their VIDs,the apparatus comprising: an array of multiple PEs each having local PEmemory; a DMA controller; and a memory maintained in the DMA controllerfor storing a processing element VID-to-PID table mapping processingelement VIDs to processing element PIDs utilized by the DMA controllerto access local memories according to their VIDs.
 2. The apparatus ofclaim 1 wherein said memory is maintained in a core transfer unit of theDMA controller.
 3. The apparatus of claim 2 wherein the core transferunit (CTU) further comprises an address generation unit (AGU) whichreceives a CTU transfer instruction which specifies a starting addresswhich is used by the AGU to generate an initial VID.
 4. The apparatus ofclaim 3 wherein the initial VID controls the selection of one of theelements of the VID-to-PID lookup table through a multiplexer.
 5. Theapparatus of claim 4 further comprising a DMA bus for providing theselected PID as a first component of a PE address.
 6. The apparatus ofclaim 5 wherein the AGU further operates to generate a PE memory offsetwhich is sent as a second component of a PE address on the DMA bus. 7.The apparatus of claim 6 further comprising a local memory interfaceunit (LMIU) which is used to compare the PID sent on the DMA bus to astored PID for any DMA access, if a match is detected then the LMIUaccepts the access.
 8. The apparatus of claim 3 wherein successive VIDsare generated in recursive fashion by the AGU.
 9. The apparatus of claim3 wherein successive VIDs are generated in recursive fashion by the AGU,and further comprising: a local memory interface unit for eachprocessing element (PE) storing a VID for each PE.
 10. The apparatus ofclaim 9 wherein a VID available to a particular LMIU or a DMA bus iscompared with the stored VID in the LMIU and where a match occurs theLMIU accepts the access.
 11. The apparatus of claim 1 wherein theVID-to-PID table is stored in a programmable register and theprogrammable register is loaded utilizing a DMA instruction.
 12. Theapparatus of claim 1 wherein the VID-to-PID table is stored in aprogrammable register and the programmable register loaded utilizing adirect write to the programmable register.
 13. A processing apparatuscomprising: a plurality of processing elements (PEs) communicativelyconnected by a bus, each PE comprising a register storing anvirtualidentification number (V ID) identifying the PE; and a direct memoryaccess (DMA) controller connected to the bus for accessing local datamemory of the PEs, each data access at least partially identified by a VID; wherein during a common data to access multiple PEs, a PE respondsto the data access if the V ID stored in the register matches the V IDof the data access.
 14. The processing apparatus of claim 13 whereineach PE comprises a local memory interface unit (LMIU) which includesthe register storing the V ID.
 15. The processing apparatus of claim 13wherein the data access is a read access.
 16. The processing apparatusof claim 13 wherein the data access is a write access.
 17. Theprocessing apparatus of claim 13 further comprising: means for updatingthe register.
 18. The processing apparatus of claim 13 whereinidentification number is a virtual identification number.